A recent LLVM commit broke a floating-point narrowing optimization in the RISC-V backend, causing ~24% regression by emitting slower double-precision division (33-cycle latency) instead of single-precision (19 cycles). A patch extending getMinimumFPType with range analysis to recognize fptrunc(uitofp) patterns restored the optimization and performance parity with GCC on the SiFive P550 CPU.
Infrastructure
Tracking down a 25% Regression on LLVM RISC-V
A lost floating-point narrowing optimization cost LLVM RISC-V 25% performance (33-cycle double vs 19-cycle single-precision division); range analysis fix restores parity with GCC on SiFive P550.
Monday, April 13, 2026 12:00 PM UTC2 MIN READSOURCE: Hacker NewsBY sys://pipeline
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infrastructure